MT46H16M32LFCX-5:B Micron Technology Inc, MT46H16M32LFCX-5:B Datasheet - Page 42

• Manufacturer Part Number: MT46H16M32LFCX-5:B
• Description: IC DDR SDRAM 512MBIT 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H16M32LFCX-5:B

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 125mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Truth Tables
Table 18: Truth Table – Current State Bank n – Command to Bank n
Notes 1–6 apply to all parameters in this table
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
Current State
Any
Idle
Row active
Read (auto pre-
charge disabled)
Write (auto pre-
charge disabled)
CS#
Notes:
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS#
1. This table applies when CKE
2. This table is bank-specific, except where noted (for example, the current state is for a
3. Current state definitions:
4. The states listed below must not be interrupted by a command issued to the same bank.
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
the previous state was self refresh), after
down, or a full initialization if the previous state was deep power-down).
specific bank and the commands shown are supported for that bank when in that state).
Exceptions are covered in the notes below.
Idle: The bank has been precharged, and
Row active: A row in the bank has been activated, and
accesses and no register accesses are in progress.
Read: A READ burst has been initiated with auto precharge disabled and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and has not yet
terminated or been terminated.
COMMAND INHIBIT or NOP commands, or supported commands to the other bank,
must be issued on any clock edge occurring during these states. Supported commands to
any other bank are determined by that bank’s current state.
Precharging: Starts with registration of a PRECHARGE command and ends when
met. After
Row activating: Starts with registration of an ACTIVE command and ends when
met. After
CAS#
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
t
t
RP is met, the bank will be in the idle state.
RCD is met, the bank will be in the row active state.
WE# Command/Action
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
42
n - 1
512Mb: x16, x32 Mobile LPDDR SDRAM
was HIGH, CKE
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
XP has been met (if the previous state was power-
t
RP has been met.
n
is HIGH and after
t
RCD has been met. No data bursts/
© 2004 Micron Technology, Inc. All rights reserved.
t
XSR has been met (if
Truth Tables
Notes
t
10, 12
10, 11
RCD is
8, 11
t
RP is
10
10
10
10
7
7
8
8
9