MT46H16M32LFCX-5:B Micron Technology Inc, MT46H16M32LFCX-5:B Datasheet - Page 69

• Manufacturer Part Number: MT46H16M32LFCX-5:B
• Description: IC DDR SDRAM 512MBIT 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H16M32LFCX-5:B

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 125mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DQ (First data no longer valid)
Figure 31: Data Output Timing –
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
DQ (First data no longer valid)
DQ and DQS, collectively
DQS0/DQS1/DQS2/DQS3
DQ (Last data valid)
DQ (Last data valid)
Notes:
CK#
DQ
DQ
DQ
DQ
DQ
DQ
CK
6,7
4
4
4
4
4
4
4
4
T1
1.
2. DQ transitioning after DQS transitions define the
3.
4. Byte 0 is DQ[7:0], byte 1 is DQ[15:8], byte 2 is DQ[23:16], byte 3 is DQ[31:24].
5.
6. The data valid window is derived for each DQS transition and is
7. DQ[7:0] and DQS0 for byte 0; DQ[15:8] and DQS1 for byte 1; DQ[23:16] and DQS2 for
t
t
DQS transition and ends with the last valid DQ transition.
t
byte 2; DQ[31:23] and DQS3 for byte 3.
t
HP
HP is the lesser of
DQSQ is derived at each DQS clock edge and is not cumulative over time; it begins with
QH is derived from
1
t
DQSQ,
t
HP
t
DQSQ
1
t
QH
t
QH, and Data Valid Window (x32)
T2
Data valid
5
2,3
window
t
CL or
t
T2
T2
T2
HP:
t
HP
1
t
t
t
QH =
DQSQ
CH clock transition collectively when a bank is active.
69
T2n
t
QH
Data valid
5
window
2,3
t
512Mb: x16, x32 Mobile LPDDR SDRAM
t
HP -
T2n
T2n
T2n
HP
1
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T3
QHS.
t
DQSQ
t
QH
t
5
2,3
Data valid
HP
window
1
T3
T3
T3
T3n
t
DQSQ window.
t
DQSQ
t
t
HP
QH
1
5
Data valid
2,3
window
T4
T3n
T3n
T3n
© 2004 Micron Technology, Inc. All rights reserved.
t
READ Operation
QH -
t
DQSQ.