MT46H16M32LFCX-5:B Micron Technology Inc, MT46H16M32LFCX-5:B Datasheet - Page 90

IC DDR SDRAM 512MBIT 90VFBGA

MT46H16M32LFCX-5:B

Manufacturer Part Number
MT46H16M32LFCX-5:B
Description
IC DDR SDRAM 512MBIT 90VFBGA
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet

Specifications of MT46H16M32LFCX-5:B

Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
512M (16M x 32)
Speed
200MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-VFBGA
Organization
16Mx32
Density
512Mb
Address Bus
15b
Access Time (max)
6.5/5ns
Maximum Clock Rate
200MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
125mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT46H16M32LFCX-5:B
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT46H16M32LFCX-5:B
Manufacturer:
MICRON
Quantity:
20 000
Part Number:
MT46H16M32LFCX-5:B TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
SELF REFRESH Operation
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
The SELF REFRESH command can be used to retain data in the device while the rest of
the system is powered down. When in self refresh mode, the device retains data without
external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command, except that CKE is disabled (LOW). All command and address input signals
except CKE are “Don’t Care” during self refresh.
During self refresh, the device is refreshed as defined in the extended mode register.
(see Partial-Array Self Refresh (page 56).) An internal temperature sensor adjusts the
refresh rate to optimize device power consumption while ensuring data integrity. (See
Temperature-Compensated Self Refresh (page 55).)
The procedure for exiting self refresh requires a sequence of commands. First, CK must
be stable prior to CKE going HIGH. When CKE is HIGH, the device must have NOP com-
mands issued for
During SELF REFRESH operation, refresh intervals are scheduled internally and may
vary. These refresh intervals may differ from the specified
the SELF REFRESH command must not be used as a substitute for the AUTO REFRESH
command.
t
XSR to complete any internal refresh already in progress.
90
512Mb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
SELF REFRESH Operation
t
REFI time. For this reason,
© 2004 Micron Technology, Inc. All rights reserved.

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