OM11043 NXP Semiconductors, OM11043 Datasheet - Page 19

DEVELOPMENT BOARD LPC1768 MBED

OM11043

Manufacturer Part Number
OM11043
Description
DEVELOPMENT BOARD LPC1768 MBED
Manufacturer
NXP Semiconductors
Series
mbedr
Type
MCUr
Datasheets

Specifications of OM11043

Contents
Board and software
Development Tool Type
Hardware / Software - Eval/Demo Board
Kit Contents
Board Cable Docs
Mcu Supported Families
LPC1000
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Silicon Manufacturer
NXP
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
LPC17xx
Silicon Family Name
LPC17xx
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
LPC1768
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4916

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
OM11043
Manufacturer:
NXP
Quantity:
103
NXP Semiconductors
LPC1769_68_67_66_65_64_63
Product data sheet
7.6 Memory map
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to 8 regions each of which can be
divided into 8 subregions. Accesses to memory locations that are not defined in the MPU
regions, or not permitted by the region setting, will cause the Memory Management Fault
exception to take place.
The LPC17xx incorporates several distinct memory regions, shown in the following
figures.
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
Figure 4
All information provided in this document is subject to legal disclaimers.
shows the overall map of the entire address space from the user
Rev. 6.01 — 11 March 2011
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2011. All rights reserved.
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