OM11043 NXP Semiconductors, OM11043 Datasheet - Page 41

• Manufacturer Part Number: OM11043
• Description: DEVELOPMENT BOARD LPC1768 MBED
• Manufacturer: NXP Semiconductors
• Series: mbedr
• Type: MCUr

Specifications of OM11043

• Contents: Board and software
• Development Tool Type: Hardware / Software - Eval/Demo Board
• Kit Contents: Board Cable Docs
• Mcu Supported Families: LPC1000
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Silicon Manufacturer: NXP
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: LPC17xx
• Silicon Family Name: LPC17xx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: LPC1768
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4916

NXP Semiconductors
LPC1769_68_67_66_65_64_63
Product data sheet
7.30.5 AHB multilayer matrix
7.30.6 External interrupt inputs
7.30.7 Memory mapping control
7.31 Emulation and debugging
The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code)
and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main
(32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these
memories. The peripheral DMA controllers, Ethernet, and USB can access all SRAM
blocks. Additionally, the matrix connects the CPU system bus and all of the DMA
controllers to the various peripheral functions.
The LPC17xx include up to 46 edge sensitive interrupt inputs combined with up to four
level sensitive external interrupt inputs as selectable pin functions. The external interrupt
inputs can optionally be used to wake up the processor from Power-down mode.
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address
space. The vector table must be located on a 128 word (512 byte) boundary because the
NVIC on the LPC17xx is configured for 128 total interrupts.
Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four
watch points.
All information provided in this document is subject to legal disclaimers.
Rev. 6.01 — 11 March 2011
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2011. All rights reserved.
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