OM11043 NXP Semiconductors, OM11043 Datasheet - Page 23

• Manufacturer Part Number: OM11043
• Description: DEVELOPMENT BOARD LPC1768 MBED
• Manufacturer: NXP Semiconductors
• Series: mbedr
• Type: MCUr

Specifications of OM11043

• Contents: Board and software
• Development Tool Type: Hardware / Software - Eval/Demo Board
• Kit Contents: Board Cable Docs
• Mcu Supported Families: LPC1000
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Silicon Manufacturer: NXP
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: LPC17xx
• Silicon Family Name: LPC17xx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: LPC1768
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4916

NXP Semiconductors
LPC1769_68_67_66_65_64_63
Product data sheet
7.10.1 Features
7.11.1 Features
7.11 Ethernet
Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can
be programmed to generate an interrupt on a rising edge, a falling edge, or both. The
edge detection is asynchronous, so it may operate when clocks are not present such as
during Power-down mode. Each enabled interrupt can be used to wake up the chip from
Power-down mode.
Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The
Ethernet block supports bus clock rates of up to 100 MHz (LPC1768/67/66/64) or 120
MHz (LPC1769). See
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus
through the AHB-multilayer matrix to access the various on-chip SRAM blocks for
Ethernet data, control, and status information.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII
(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial
bus.
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Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
Pull-up/pull-down resistor configuration and open-drain configuration can be
programmed through the pin connect block for each GPIO pin.
Ethernet standards support:
– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x full duplex flow control and half duplex back pressure.
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support.
Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.
100 Base-FX, and 100 Base-T4.
All information provided in this document is subject to legal disclaimers.
Table
Rev. 6.01 — 11 March 2011
2.
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2011. All rights reserved.
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