OM11043 NXP Semiconductors, OM11043 Datasheet - Page 32

• Manufacturer Part Number: OM11043
• Description: DEVELOPMENT BOARD LPC1768 MBED
• Manufacturer: NXP Semiconductors
• Series: mbedr
• Type: MCUr

Specifications of OM11043

• Contents: Board and software
• Development Tool Type: Hardware / Software - Eval/Demo Board
• Kit Contents: Board Cable Docs
• Mcu Supported Families: LPC1000
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Silicon Manufacturer: NXP
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: LPC17xx
• Silicon Family Name: LPC17xx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: LPC1768
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4916

NXP Semiconductors
LPC1769_68_67_66_65_64_63
Product data sheet
7.25.1 Features
7.27.1 Features
7.25 Repetitive Interrupt (RI) timer
7.26 ARM Cortex-M3 system tick timer
7.27 Watchdog timer
The repetitive interrupt timer provides a free-running 32-bit counter which is compared to
a selectable value, generating an interrupt when a match occurs. Any bits of the
timer/compare can be masked such that they do not contribute to the match detection.
The repetitive interrupt timer can be used to create an interrupt that repeats at
predetermined intervals.
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval. In the LPC17xx, this timer can be
clocked from the internal AHB clock or from a device pin.
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
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Digital filter with programmable delays for encoder input signals.
Can accept decoded signal inputs (clk and direction).
Connected to APB.
32-bit counter running from PCLK. Counter can be free-running or be reset by a
generated interrupt.
32-bit compare value.
32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal prescaler.
Selectable time period from (T
multiples of T
The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC)
oscillator, the RTC oscillator, or the APB peripheral clock. This gives a wide range of
potential timing choices of Watchdog operation under different power reduction
All information provided in this document is subject to legal disclaimers.
cy(WDCLK)
Rev. 6.01 — 11 March 2011
× 4.
LPC1769/68/67/66/65/64/63
cy(WDCLK)
× 256 × 4) to (T
32-bit ARM Cortex-M3 microcontroller
cy(WDCLK)
× 2
© NXP B.V. 2011. All rights reserved.
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