AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 280
![IC MCU AVR32 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0128-ALUT
Manufacturer Part Number
AT32UC3A0128-ALUT
Description
IC MCU AVR32 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128-ALUT
Manufacturer:
Atmel
Quantity:
166
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25.9.4
Name:
Access Type:
Offset:
Reset value:
• FSLENHI: Receive Frame Sync Length High part
The four MSB of the FSLEN bitfield.
• FSEDGE: Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
• FSOS: Receive Frame Sync Output Selection
• FSLEN: Receive Frame Sync Length
This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive
Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also deter-
mines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. Note: The four most
significant bits fo this bitfield are in the FSLENHI bitfield.
Pulse length is equal to ({FSLENHI,FSLEN} + 1) Receive Clock periods. Thus, if {FSLENHI,FSLEN} is 0, the Receive
Frame Sync signal is generated during one Receive Clock period.
• DATNB: Data Number per Frame
32058J-AVR32-04/11
MSBF
0x6-0x7
31
23
15
FSOS
–
–
7
0x0
0x1
0x2
0x3
0x4
0x5
FSEDGE
Receive Frame Mode Register
0x0
0x1
Selected Receive Frame Sync Signal
None
Negative Pulse
Positive Pulse
Driven Low during data transfer
Driven High during data transfer
Toggling at each start of data transfer
Reserved
30
22
14
RFMR
Read/Write
0x14
0x00000000
–
6
–
Frame Sync Edge Detection
Positive Edge Detection
Negative Edge Detection
FSLENHI
FSOS
LOOP
29
21
13
–
5
28
20
12
–
4
27
19
11
–
3
DATLEN
26
18
10
–
2
FSLEN
DATNB
RX_FRAME_SYNC Pin
25
17
–
9
1
AT32UC3A
Undefined
Input-only
Output
Output
Output
Output
Output
FSEDGE
24
16
8
0
280
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