AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 681
![IC MCU AVR32 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0128-ALUT
Manufacturer Part Number
AT32UC3A0128-ALUT
Description
IC MCU AVR32 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0128-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128-ALUT
Manufacturer:
Atmel
Quantity:
166
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32.6.3
32.6.3.1
32.6.3.2
32.6.3.3
32058J–AVR32–04/11
PWM Controller Operations
Initialization
Changing the Duty Cycle or the Period
Source Clock Selection Criteria
Before enabling the output channel, this channel must have been configured by the software
application:
• Configuration of the clock generator if DIVA and DIVB are required
• Selection of the clock for each channel (CPRE field in the CMRx register)
• Configuration of the waveform alignment for each channel (CALG field in the CMRx register)
• Configuration of the period for each channel (CPRD in the CPRDx register). Writing in CPRDx
• Configuration of the duty cycle for each channel (CDTY in the CDTYx register). Writing in
• Configuration of the output waveform polarity for each channel (CPOL in the CMRx register)
• Enable Interrupts (Writing CHIDx in the IER register)
• Enable the PWM channel (Writing CHIDx in the ENA register)
It is possible to synchronize different channels by enabling them at the same time by means of
writing simultaneously several CHIDx bits in the ENA register.
In such a situation, all channels may have the same clock selector configuration and the same
period specified.
The large number of source clocks can make selection difficult. The relationship between the
value in the Period Register (CPRDx) and the Duty Cycle Register (CDTYx) can help the user in
choosing. The event number written in the Period Register gives the PWM accuracy. The Duty
Cycle quantum cannot be lower than 1/CPRDx value. The higher the value of CPRDx, the
greater the PWM accuracy.
For example, if the user sets 15 (in decimal) in CPRDx, the user is able to set a value between 1
up to 14 in CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the
PWM period.
It is possible to modulate the output waveform duty cycle or period.
To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx)
to change waveform parameters while the channel is still enabled. The user can write a new
period value or duty cycle value in the update register (CUPDx). This register holds the new
value until the end of the current cycle and updates the value for the next cycle. Depending on
the CPD field in the CMRx register, CUPDx either updates CPRDx or CDTYx. Note that even if
the update register is used, the period must not be smaller than the duty cycle.
Register is possible while the channel is disabled. After validation of the channel, the user must
use CUPDx Register to update CPRDx as explained below.
CDTYx Register is possible while the channel is disabled. After validation of the channel, the
user must use CUPDx Register to update CDTYx as explained below.
AT32UC3A
681
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