AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 755

IC MCU AVR32 128KB FLASH 144LQFP

AT32UC3A0128-ALUT

Manufacturer Part Number
AT32UC3A0128-ALUT
Description
IC MCU AVR32 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A0128-ALUT

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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36.9.6
32058J–AVR32–04/11
MEMORY_BLOCK_ACCESS
Note: This instruction was previously known as MEMORY_ACCESS, and is provided for back-
wards compatibility.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the MEMORY_WORD_ACCESS instruction is
selected, and toggles between address and data mode each time a data scan completes with
the busy bit cleared.
Starting in Run-Test/Idle, SAB data are accessed in the following way:
For any operation, the full 34 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
Table 36-9.
This instruction allows access to the entire SAB data area. Up to 32 bits of data are accessed at
a time, while the address is sequentially incremented from the previously used address.
In this mode, the SAB address, size, and access direction is not provided with each access.
Instead, the previous address is auto-incremented depending on the specified size and the pre-
v i o u s o p e r a t i o n r e p e a t e d . T h e a d d r e s s m u s t b e s e t u p i n a d v a n c e w i t h
MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS. It is allowed, but not required, to
shift data after shifting the address.
This instruction is primarily intended to speed up large quantities of sequential word accesses. It
is possible to use it also for byte and halfword accesses, but the overhead in this is case much
larger as 32 bits must still be shifted for each access.
The following sequence should be used:
Instructions
IR input value
IR output value
DR Size
DR input value (Address phase)
DR input value (Data read phase)
DR input value (Data write phase)
DR output value (Address phase)
DR output value (Data read phase)
DR output value (Data write phase)
1. Select the DR Scan path.
2. Scan in the 34-bit address of the data to access, and a direction bit (1=read, 0=write).
3. Go to Update-DR and re-enter Select-DR Scan.
4. For a read operation, scan out the contents of the addressed area. For a write opera-
5. Return to Run-Test/Idle.
tion, scan in the new contents of the area.
MEMORY_WORD_ACCESS details
Details
10001 (0x11)
peb01
35 bits
aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aar
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxx
dddddddd dddddddd dddddddd dddddddd xxx
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb
xeb dddddddd dddddddd dddddddd dddddddd
xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
AT32UC3A
755

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