AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 526

IC MCU AVR32 128KB FLASH 144LQFP

AT32UC3A0128-ALUT

Manufacturer Part Number
AT32UC3A0128-ALUT
Description
IC MCU AVR32 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A0128-ALUT

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
AT32UC3A0128-ALUT
Manufacturer:
Atmel
Quantity:
166
Price:
Figure 30-25. Example of an IN Pipe with 1 Data Bank
Figure 30-26. Example of an IN Pipe with 2 Data Banks
30.7.3.11
32058J–AVR32–04/11
RXINI
FIFOCON
IN
Management of OUT Pipes
RXINI
FIFOCON
(bank 0)
IN
DATA
OUT packets are sent by the host. All the data can be written by the firmware which acknowl-
edges or not the bank when it is full.
The pipe must be configured and unfrozen first.
The TXOUTI bit is set by hardware at the same time as FIFOCON when the current bank is free.
This triggers a PXINT interrupt if TXOUTE = 1.
TXOUTI shall be cleared by software (by setting the TXOUTIC bit) to acknowledge the interrupt,
what has no effect on the pipe FIFO.
The firmware then writes into the FIFO and clears the FIFOCON bit to allow the USB controller
to send the data. If the OUT pipe is composed of multiple banks, this also switches to the next
bank. The TXOUTI and FIFOCON bits are updated by hardware in accordance with the status of
the next bank.
TXOUTI shall always be cleared before clearing FIFOCON.
The RWALL bit is set by hardware when the current bank is not full, i.e. the software can write
further data into the FIFO.
Note that if the firmware decides to switch to the Suspend state (by clearing the SOFE bit) while
a bank is ready to be sent, the USB controller automatically exits this state and the bank is sent.
(bank 0)
DATA
HW
ACK
SW
read data from CPU
HW
ACK
BANK 0
SW
read data from CPU
IN
BANK 0
SW
(bank 1)
IN
DATA
SW
(bank 0)
DATA
HW
ACK
read data from CPU
SW
HW
ACK
BANK 1
read data from CPU
AT32UC3A
SW
BANK 0
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