R5F21258SNFP#U0 Renesas Electronics America, R5F21258SNFP#U0 Datasheet - Page 149

• Manufacturer Part Number: R5F21258SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21258SNFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 2.2V To 5.5V
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: YMCRPR8C25 - REF PLATFORM MOTOR CTRL R8C/25R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
13.1
Table 13.2
NOTES:
Count source
Count operation
Period
Count start condition
Reset condition of watchdog
timer
Count stop condition
Operation at time of underflow
The count source of the watchdog timer is the CPU clock when count source protection mode is disabled.
Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled).
1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. The prescaler is
2. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the
prescaler.
0FFFFh with a flash programmer.
Count Source Protection Mode Disabled
Feb 29, 2008
Item
Watchdog Timer Specifications (with Count Source Protection Mode Disabled)
Page 130 of 485
CPU clock
Decrement
Division ratio of prescaler (n) × count value of watchdog timer (32768)
n: 16 or 128 (selected by WDC7 bit in WDC register)
Example: When the CPU clock frequency is 16 MHz and prescaler
The WDTON bit
of the watchdog timer after a reset
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
• When the WDTON bit is set to 0 (watchdog timer starts automatically
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Stop and wait modes (inherit the count from the held value after exiting
modes)
• When the PM12 bit in the PM1 register is set to 0
• When the PM12 bit in the PM1 register is set to 1
reset)
after exiting)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
The watchdog timer and prescaler start counting automatically after a
reset
Watchdog timer interrupt
Watchdog timer reset (refer to 5.6 Watchdog Timer Reset)
divided by 16, the period is approximately 32.8 ms
(2)
in the OFS register (0FFFFh) selects the operation
Specification
CPU clock
13. Watchdog Timer
(1)