R5F21258SNFP#U0 Renesas Electronics America, R5F21258SNFP#U0 Datasheet - Page 345

• Manufacturer Part Number: R5F21258SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21258SNFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 2.2V To 5.5V
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: YMCRPR8C25 - REF PLATFORM MOTOR CTRL R8C/25R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 16.17
NOTE:
(4)
(5)
(1)
(2)
(3)
(6)
Feb 29, 2008
1. Write 0 after reading 1 to set the TEND bit to 0.
SSSR register
SSER register
Communication Mode)
Sample Flowchart of Data Transmission/Reception (Clock Synchronous
Write transmit data to SSTDR register
Read receive data in SSRDR register
Read TDRE bit in SSSR register
Read RDRF bit in SSSR register
Read TEND bit in SSSR register
No
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transmission
RDRF = 1 ?
TEND = 1 ?
Initialization
TDRE = 1 ?
continues?
Start
Data
End
TEND bit ← 0
RE bit ← 0
TE bit ← 0
Yes
Yes
No
Yes
(2)
No
No
(1)
Yes
(2) Confirm that the RDRF bit is set to 1. If the RDRF
(3) Determine whether the data transmission
(4) When the data transmission is completed, the
(5) Set the TEND bit to 0 and bits RE and TE in
(6) the SSER register to 0 before ending transmit/
(1) After reading the SSSR register and confirming
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
continues
TEND bit in the SSSR register is set to 1.
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
bit is automatically set to 0.
receive mode.
16. Clock Synchronous Serial Interface