R5F21258SNFP#U0 Renesas Electronics America, R5F21258SNFP#U0 Datasheet - Page 409

IC R8C/25 MCU FLASH 52LQFP

R5F21258SNFP#U0

Manufacturer Part Number
R5F21258SNFP#U0
Description
IC R8C/25 MCU FLASH 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Datasheets

Specifications of R5F21258SNFP#U0

Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Core Processor
R8C
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
2.2V To 5.5V
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
YMCRPR8C25 - REF PLATFORM MOTOR CTRL R8C/25R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Part Number
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Price
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RENESAS
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R5F21258SNFP#U0R5F21258SNFP
0
Company:
Part Number:
R5F21258SNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
18.2
Table 18.3
Function
Start conditions
Stop condition
Interrupt request generation
timing
Input pin
Reading of result of A/D
converter
In repeat mode, the input voltage of one selected pin is A/D converted repeatedly.
Table 18.3 lists the Repeat Mode Specifications. Figures 18.6 and 18.7 show Registers ADCON0 and ADCON1 in
Repeat Mode.
Repeat Mode
Feb 29, 2008
Item
Repeat Mode Specifications
Page 390 of 485
The Input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is
A/D converted repeatedly
• When the ADCAP bit is set to 0 (software trigger):
• When the ADCAP bit is set to 1 (starts in timer RD (complementary PWM
Set the ADST bit to 0
Not generated
Select one of AN0 to AN11
Read AD register
mode)):
Set the ADST bit to 1 (A/D conversion starts)
A compare match between registers TRD0 and TRDGRA0 or a TRD1
underflow is generated while the ADST bit is set to 1
Specification
18. A/D Converter

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