R5F21258SNFP#U0 Renesas Electronics America, R5F21258SNFP#U0 Datasheet - Page 84

• Manufacturer Part Number: R5F21258SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21258SNFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 2.2V To 5.5V
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: YMCRPR8C25 - REF PLATFORM MOTOR CTRL R8C/25R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Table 7.27
X: 0 or 1
NOTES:
Table 7.28
X: 0 or 1
NOTE:
Table 7.29
X: 0 or 1
NOTE:
Table 7.30
X: 0 or 1
NOTES:
Register
Register
Register
Setting
Value
Setting
Setting
Register
Value
Value
Setting
Bit
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR7 bit in the P2DRR register to 1.
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
Value
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the SOOS bit in the SSMR2 register to 1 when this pin functions as output.
Bit
Bit
Bit
Feb 29, 2008
PD2_7
PD2
X
X
X
X
0
1
0
PD3_3
PD3_1
PD3
PD3
Port P2_7/TRDIOD1
Port P3_0/TRAO
Port P3_1/TRBO
Port P3_3/SSI
0
1
X
X
PD3_0
0
1
X
X
TRDOER1
PD3
X
0
1
ED1
1
1
X
0
0
0
0
Clock Synchronous Serial I/O with Chip Select
SSI output control
(Refer to Table 16.4 Association between
Page 65 of 485
Communication Modes and I/O Pins.)
TMOD1
CMD1
X
X
0
1
1
0
0
0
0
0
Other than 00b
X
X
0
0
0
1
TRDFCR
TRAIOC
TRBMR
TOENA
CMD0 PWM3
01b
X
X
0
0
1
1
0
0
0
0
1
TMOD0
X
X
X
X
1
1
1
0
0
SSI input control
Input port
Output port
TRAO output
TRDPMR
PWMD1
X
X
X
X
0
1
0
X
X
0
0
1
0
TRBIOC
TOCNT
(1)
X
X
1
0
IOD2 IOD1 IOD0
X
X
X
X
X
1
0
0
TRDIORC1
X
X
X
X
X
X
0
1
Input port
Output port
TRBO output
IICSEL
PMR
0
1
0
1
0
0
X
X
X
X
X
X
X
1
(1)
Input port
Output port
SSI input
SSI output
Input port
Output port
Timer mode (input capture function)
Complementary PWM mode waveform
output
Reset synchronous PWM mode waveform
output
PWM mode waveform output
Timer mode waveform output
(output compare function)
Function
(2)
(2)
(1)
(1)
(2)
(2)
(2)
Function
7. Programmable I/O Ports
Function
Function
(2)
(2)