R5F21258SNFP#U0 Renesas Electronics America, R5F21258SNFP#U0 Datasheet - Page 333

• Manufacturer Part Number: R5F21258SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21258SNFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 2.2V To 5.5V
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: YMCRPR8C25 - REF PLATFORM MOTOR CTRL R8C/25R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 16.8
Figure 16.9
SS Transmit Data Register
SS Receive Data Register
Port Mode Register
b7 b6 b5 b4
b7 b6 b5 b4
NOTE:
b7 b6 b5 b4
1. The SSRDR register retains the data received before an overrun error occurs (ORER bit in the SSSR register set to 1
0 0
(overrun error)). When an overrun error occurs, the receive data may contain errors and therefore should be
discarded.
Feb 29, 2008
b3
b3 b2 b1 b0
b3 b2
0
b2
0
PMR Register
Registers SSTDR and SSRDR
b1
b1
0
b0
b0
0
Store the transmit data.
The stored transmit data is transferred to the SSTRSR register and transmission is started
w hen it is detected that the SSTRSR register is empty.
When the next transmit data is w ritten to the SSTDR register during the data transmission from
the SSTRSR register, the data can be transmitted continuously.
When the MLS bit in the SSMR register is set to 1 (transfer data w ith LSB-first), the data in
w hich MSB and LSB are reversed is read, after w riting to the SSTDR register.
Store the receive data.
The receive data is transferred to the SSRDR register and the receive operation is completed
w hen 1 byte of data has been received by the SSTRSR register. At this time, the next receive
operation is possible. Continuous reception is possible using registers SSTRSR and SSRDR.
Bit Symbol
U1PINSEL
(b3-b0)
(b6-b5)
Symbol
SSTDR
Symbol
SSRDR
Symbol
IICSEL
PMR
Page 314 of 485
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Reserved bits
Port CLK1/TXD1/RXD1 sw itch bit
Reserved bits
SSU / I
2
C bus sw itch bit
(1)
Address
Bit Name
Address
Address
00F8h
00BEh
00BFh
Function
Function
Set to 0.
0 : I/O ports P6_5, P6_6, P6_7
1 : CLK1, TXD1, RXD1
Set to 0.
0 : Selects SSU function
1 : Selects I
16. Clock Synchronous Serial Interface
2
C bus function
After Reset
After Reset
After Reset
Function
00h
FFh
FFh
RW
RW
RW
RW
RW
RW
RO
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