MC68HC908JL8CSPE Freescale Semiconductor, MC68HC908JL8CSPE Datasheet - Page 135

• Manufacturer Part Number: MC68HC908JL8CSPE
• Description: IC MCU 8K FLASH 8MHZ 32-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL8CSPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

M — Mode (Character Length) Bit
WAKE — Wakeup Condition Bit
ILTY — Idle Line Type Bit
PEN — Parity Enable Bit
PTY — Parity Bit
Freescale Semiconductor
This read/write bit determines whether SCI characters are eight or nine bits long. (See
ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the
M bit.
This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most
significant bit position of a received character or an idle condition on the RxD pin. Reset clears the
WAKE bit.
This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The counting
begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string
of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count
after the stop bit avoids false idle character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
This read/write bit enables the SCI parity function. (See
inserts a parity bit in the most significant bit position. (See
This read/write bit determines whether the SCI generates and checks for odd parity or even parity.
(See
1 = 9-bit SCI characters
0 = 8-bit SCI characters
1 = Address mark wakeup
0 = Idle line wakeup
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
1 = Parity function enabled
0 = Parity function disabled
1 = Odd parity
0 = Even parity
Table
9-5.) Reset clears the PTY bit.
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
M
0
1
0
0
1
1
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
Control Bits
PEN and PTY
0X
0X
10
11
10
11
Table 9-5. Character Format Selection
Start
Bits
1
1
1
1
1
1
Data
Bits
NOTE
8
9
7
7
8
8
Character Format
Parity
None
None
Even
Even
Table
Odd
Odd
Figure
9-5.) When enabled, the parity function
9-3.) Reset clears the PEN bit.
Stop
Bits
1
1
1
1
1
1
Character
Length
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
Table
I/O Registers
9-5.) The
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