MC68HC908JL8CSPE Freescale Semiconductor, MC68HC908JL8CSPE Datasheet - Page 63

• Manufacturer Part Number: MC68HC908JL8CSPE
• Description: IC MCU 8K FLASH 8MHZ 32-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL8CSPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, OSCOUT, as shown in
5.2.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency divided by four.
5.2.2 Clock Start-Up from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 ICLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks
start upon completion of the timeout.
5.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows ICLK to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay time-out. This time-out is
selectable as 4096 or 32 ICLK cycles. (See
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
Freescale Semiconductor
$FE04
$FE05
$FE06
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Status Register 3
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
(INT1)
(INT2)
(INT3)
OSCOUT is OSC frequency divided by 2
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 5-2. SIM I/O Register Summary
OSCILLATOR
OSCILLATOR
IF14
From
From
IF6
Figure 5-3. SIM Clock Signals
R
R
R
0
0
0
0
= Unimplemented
5.6.2 Stop
IF13
IF5
R
R
R
0
0
0
0
OSCOUT
ICLK
IF12
IF4
R
R
R
0
0
0
0
Mode.)
SIM COUNTER
÷ 2
IF11
IF3
R
R
R
0
0
0
0
SIM
GENERATORS
BUS CLOCK
SIM Bus Clock Control and Generation
R
R
R
R
0
0
0
0
0
0
Figure
= Reserved
IF1
R
R
R
0
0
0
0
0
5-3.
IF8
R
R
R
0
0
0
0
0
IF15
IF7
R
R
R
0
0
0
0
63