MC68HC908JL8CSPE Freescale Semiconductor, MC68HC908JL8CSPE Datasheet - Page 75

• Manufacturer Part Number: MC68HC908JL8CSPE
• Description: IC MCU 8K FLASH 8MHZ 32-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL8CSPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.7 SIM Registers
The SIM has three memory mapped registers.
5.7.1 Break Status Register (BSR)
The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.
Freescale Semiconductor
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•
•
INT/BREAK
Break Status Register (BSR)
Reset Status Register (RSR)
Break Flag Control Register (BFCR)
ICLK
IAB
Address:
Reset:
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
Read:
Write:
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
Figure 5-19. Stop Mode Recovery from Interrupt or Break
R/W
IDB
IAB
instruction.
$FE00
Bit 7
R
R
0
STOP ADDR
Figure 5-20. Break Status Register (BSR)
STOP +1
= Reserved
Figure 5-18. Stop Mode Entry Timing
R
6
0
PREVIOUS DATA
STOP ADDR + 1
R
5
0
STOP + 2
STOP RECOVERY PERIOD
NEXT OPCODE
R
4
0
STOP + 2
1. Writing a logic zero clears SBSW.
R
3
0
SAME
SP
SAME
R
2
0
SP – 1
Note
SBSW
SAME
1
0
(1)
SAME
SP – 2
Bit 0
R
0
SIM Registers
SP – 3
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