MC68HC908JL8CSPE Freescale Semiconductor, MC68HC908JL8CSPE Datasheet - Page 150

• Manufacturer Part Number: MC68HC908JL8CSPE
• Description: IC MCU 8K FLASH 8MHZ 32-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL8CSPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Analog-to-Digital Converter (ADC)
10.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
10.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
ADIV[2:0] — ADC Clock Prescaler Bits
150
ADIV[2:0] form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC
clock.
approximately 1MHz.
Table 10-2
Address:
Address:
X = don’t care
Reset:
Reset:
Read:
Read:
Write:
Write:
ADIV2
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
0
0
0
0
1
shows the available clock configurations. The ADC clock should be set to
$003D
$003E
ADIV2
Bit 7
AD7
Bit 7
0
Figure 10-5. ADC Input Clock Register (ADICLK)
ADIV1
Figure 10-4. ADC Data Register (ADR)
ADIV1
X
0
0
1
1
AD6
Table 10-2. ADC Clock Divide Ratio
6
6
0
= Unimplemented
= Unimplemented
ADIV0
AD5
5
5
0
ADIV0
X
0
1
0
1
Indeterminate after reset
AD4
4
4
0
0
AD3
3
3
0
0
Bus Clock ÷ 1
Bus Clock ÷ 2
Bus Clock ÷ 4
Bus Clock ÷ 8
Bus Clock ÷ 16
ADC Clock Rate
AD2
2
2
0
0
AD1
1
1
0
0
Freescale Semiconductor
Bit 0
AD0
Bit 0
0
0