MC68HC908JL8CSPE Freescale Semiconductor, MC68HC908JL8CSPE Datasheet - Page 61

• Manufacturer Part Number: MC68HC908JL8CSPE
• Description: IC MCU 8K FLASH 8MHZ 32-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL8CSPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 5
System Integration Module (SIM)
5.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM
is shown in
controller that coordinates CPU and exception timing.
The SIM is responsible for:
Table 5-1
Freescale Semiconductor
•
•
•
•
•
Bus clock generation and control for CPU and peripherals
–
–
Master reset control, including power-on reset (POR) and COP timeout
Interrupt control:
–
–
–
CPU enable/disable timing
Modular architecture expandable to 128 interrupt sources
Signal Name
shows the internal signal names used in this section.
Stop/wait/reset/break entry and recovery
Internal clock control
Acknowledge timing
Arbitration control timing
Vector address generation
OSCOUT
PORRST
Figure
ICLK
IRST
R/W
IAB
IDB
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
5-1.
Figure 5-2
Internal oscillator clock
The XTAL or RC frequency divided by two. This signal is again divided by two in the SIM
to generate the internal bus clocks. (Bus clock = OSCOUT ÷ 2)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Table 5-1. Signal Name Conventions
is a summary of the SIM I/O registers. The SIM is a system state
Description
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