MC68HC908JL8CSPE Freescale Semiconductor, MC68HC908JL8CSPE Datasheet - Page 180

• Manufacturer Part Number: MC68HC908JL8CSPE
• Description: IC MCU 8K FLASH 8MHZ 32-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL8CSPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Break Module (BREAK)
16.3.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. (See
subsection for each module.)
16.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
16.3.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
16.3.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V
180
Addr.
$FE0C
$FE0D
$FE0E
$FE00 Break Status Register (BSR)
$FE03
Note: Writing a logic 0 clears SBSW.
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD
($FEFC:$FEFD in monitor mode)
Break Status and Control
Register Name
Break Address High
Break Flag Control
Break Address low
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
(BRKSCR)
Register
Register
Register
Register
(BRKH)
(BFCR)
(BRKL)
Reset:
Reset:
Reset:
Reset:
Reset:
Figure 16-2. Break I/O Register Summary
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
5.7.3 Break Flag Control Register (BFCR)
BRKE
BCFE
Bit15
Bit 7
Bit7
R
0
0
0
0
BRKA
Bit14
Bit6
= Unimplemented
R
R
6
0
0
0
TST
Bit13
Bit5
R
R
5
0
0
0
0
is present on the RST pin.
Bit12
Bit4
R
R
R
4
0
0
0
0
Bit11
Bit3
R
R
3
0
0
0
0
= Reserved
and see the Break Interrupts
Bit10
Bit2
R
R
2
0
0
0
0
Freescale Semiconductor
See note
SBSW
Bit9
Bit1
R
1
0
0
0
0
0
Bit 0
Bit8
Bit0
R
R
0
0
0
0