MC9S08AW60CPUE Freescale Semiconductor, MC9S08AW60CPUE Datasheet - Page 303

IC MCU 64K FLASH 64-LQFP

MC9S08AW60CPUE

Manufacturer Part Number
MC9S08AW60CPUE
Description
IC MCU 64K FLASH 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08AW60CPUE

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
S08AW
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
8
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AW60E
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
For Use With
DEMO9S08AW60E - DEMO BOARD FOR MC9S08AW60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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A.11
Table A-15
Freescale Semiconductor
SPI Characteristics
1
2
3
4
5
and
Num
Maximum baud rate must be limited to 5 MHz due to pad input characteristics.
Refer to
All timing is shown with respect to 20% V
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
Time to data active from high-impedance state.
Hold time to high-impedance state.
10
11
1
2
3
4
5
6
7
8
9
Figure A-16
1
Figure A-16
C
Operating frequency
Cycle time
Enable lead time
Enable lag time
Clock (SPSCK) high time
Master and Slave
Clock (SPSCK) low time Master
and Slave
Data setup time (inputs)
Data hold time (inputs)
Access time, slave
Disable time, slave
Data setup time (outputs)
Data hold time (outputs)
through
through
Characteristic
Table A-15. SPI Electrical Characteristic
Figure A-19
Figure
MC9S08AW60 Data Sheet, Rev 2
4
5
3
A-19.
2
Master
Master
Master
Master
Master
Master
Master
Master
DD
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
describe the timing requirements for the SPI system.
and 70% V
Appendix A Electrical Characteristics and Timing Specifications
Symbol
t
t
t
t
t
t
t
t
SCKH
SCKL
t
t
SI(M)
HI(M)
t
t
SI(S)
HI(S)
Lead
Lead
t
t
t
t
t
SCK
SCK
f
f
Lag
Lag
SO
SO
HO
HO
t
dis
op
op
A
DD
, unless noted; 100 pF load on all SPI
1/2 t
1/2 t
f
Bus
SCK
SCK
Min
–10
–10
1/2
1/2
dc
30
30
30
30
25
25
/2048
2
4
0
– 25
– 25
f
f
2048
Bus
Bus
Max
1/2
1/2
40
40
/2
/4
t
t
t
t
Unit
SCK
SCK
SCK
SCK
t
t
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
303

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