D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 110
![IC SUPER H MPU ROMLESS 208QFP](/photos/12/31/123145/d6417729rhf200bv_sml.jpg)
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
EVERLIGHT
Quantity:
1 000
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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The instruction code, operation, and number of execution states of the CPU instructions are shown
in the following tables, classified by instruction type, using the format shown below.
Instruction
Indicated by mnemonic.
Explanation of Symbols
OP.Sz SRC, DEST
Rm: Source register
Rn:
imm: Immediate data
disp: Displacement
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
Rev. 5.0, 09/03, page 62 of 806
OP:
Sz:
SRC: Source
DEST: Destination
Destination register
Operation code
Size
2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.
(1) When there is contention between an instruction fetch and a data access
(2) When the destination register of a load instruction (memory
instruction execution states will be increased in cases such as the following:
used by the following instruction
Instruction Code
Indicated in MSB
LSB order.
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
iiii:
dddd:
0000: R0
0001: R1
.........
1111: R15
Immediate data
Displacement *
2
Operation
Indicates summary of
operation.
Explanation of Symbols
(xx):
M/Q/T: Flag bits in SR
&:
|:
^:
~:
<<n: n-bit left shift
>>n: n-bit right shift
,
Logical AND of each bit
Logical OR of each bit
Exclusive logical OR of
each bit
Logical NOT of each bit
:
Transfer direction
Memory operand
Privilege
Indicates a
privileged
instruction.
register) is also
Execution
States
Value when
no wait
states are
inserted *
1
T Bit
Value of T bit
after
instruction is
executed
Explanation
of Symbols
—: No
change
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