D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 338

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 4 and 3—Area 2 Wait Control (A2W1, A2W0): Specify the number of wait states inserted
in physical space area 2.
Bit 4: A2W0
0
1
Bit 4: A2W1
0
1
Bits 2 to 0—Area 0 Wait Control (A0W2, A0W1, A0W0): Specify the number of wait states
inserted in physical space area 0. Also specify the burst pitch for burst transfer.
A0W2
0
1
Rev. 5.0, 09/03, page 290 of 806
Bit 2:
For Ordinary Memory
For Synchronous DRAM
Bit 1:
A0W1
0
1
0
1
Bit 0:
A0W0
0
1
0
1
0
1
0
1
Bit 3: A2W0
0
1
0
1
Bit 3: A2W0
0
1
0
1
Inserted
Wait States
0
1
2
3
4
6
8
10
(Initial value)
First Cycle
W W W W A A A A I I I I T T T T Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Inserted Wait States
0
1
2
3
Synchronous DRAM: CAS Latency
1
1
2
3
Description
Number of States
Per Data Transfer
2
2
3
4
4
6
8
10
(Initial value)
Description
Description
(Excluding First Cycle)
W W W W A A A A I I I I T T T T Pin
Ignored
Enabled
Enabled
Enabled (Initial value)
Burst Cycle
W W W W A A A A I I I I T T T T Pin
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled