D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 302

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Mode 2: The on-chip crystal oscillator operates, with the oscillation frequency being multiplied
by 4 by PLL circuit 2 before being supplied inside the chip, allowing a low crystal frequency to be
used. A crystal oscillation frequency of 6.25 MHz to 16.67 MHz can be used, and the CKIO
frequency range is 25 MHz to 66.67 MHz.
As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.
Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and
undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL
circuit 1 before being supplied to the chip. In modes 0 to 4, the system clock is generated from the
output of the chip’s CKIO pin. Consequently, if a large number of ICs are operating on the clock
cycle, the CKIO pin load will be large. This mode, however, assumes a comparatively large-scale
system. If a large number of ICs are operating on the clock cycle, a clock generator with a number
of low-skew clock outputs can be provided, so that the ICs can operate synchronously by
distributing the clocks to each one.
As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.
Table 10.4 Available Combinations of Clock Mode and FRQCR Values
Clock
Mode FRQCR PLL1
0
Rev. 5.0, 09/03, page 254 of 806
H'0100
H'0101
H'0102
H'0111
H'0112
H'0115
H'0116
H'0122
H'0126
H'012A
H'A100
H'A101
H'E100
H'E101
H'A111
ON ( 1) ON ( 1) 1:1:1
ON ( 1) ON ( 1) 1:1:1/2
ON ( 1) ON ( 1) 1:1:1/4
ON ( 2) ON ( 1) 2:1:1
ON ( 2) ON ( 1) 2:1:1/2
ON ( 2) ON ( 1) 1:1:1
ON ( 2) ON ( 1) 1:1:1/2
ON ( 4) ON ( 1) 4:1:1
ON ( 4) ON ( 1) 2:1:1
ON ( 4) ON ( 1) 1:1:1
ON ( 3) ON ( 1) 3:1:1
ON ( 3) ON ( 1) 3:1:1/2
ON ( 3) ON ( 1) 1:1:1
ON ( 3) ON ( 1) 1:1:1/2
ON ( 6) ON ( 1) 6:1:1
PLL2
Clock Rate *
(I:B:P)
Input Frequency
Range
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
CKIO Frequency
Range
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz