D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 731

IC SUPER H MPU ROMLESS 208QFP

D6417729RHF200BV

Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of D6417729RHF200BV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number:
D6417729RHF200BV
Manufacturer:
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Quantity:
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22.3
The D/A converter has two built-in D/A conversion circuits that can perform conversion
independently.
D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value
is modified, conversion of the new data begins immediately. The conversion results are output
when bits DAOE0 and DAOE1 are set to 1.
An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 22.2.
1. Data to be converted is written in DADR0.
2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The
3. If the DADR0 value is modified, conversion starts immediately, and the result is output after
4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
converted result is output after the conversion time. The output value is (DADR0 contents/256)
the DAOE0 bit is cleared to 0.
the conversion time.
φ
Address bus
DADR0
DAOE0
DA0
AVcc. Output of this conversion result continues until the value in DADR0 is modified or
Legend
t
DCONV
Operation
: D/A conversion time
write cycle
DADR0
High-impedance state
Figure 22.2 Example of D/A Converter Operation
write cycle
DACR
Conversion data 1
t
DCONV
Conversion
result 1
write cycle
DADR0
Rev. 5.0, 09/03, page 683 of 806
t
DCONV
Conversion data 2
Conversion
result 2
write cycle
DACR

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