D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 537
![IC SUPER H MPU ROMLESS 208QFP](/photos/12/31/123145/d6417729rhf200bv_sml.jpg)
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Part Number:
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SCPDR Bit 0—Serial Port Break Data (SCP0DT): Specifies the serial port RxD pin input data
and TxD pin output data. The TxD pin output condition is specified by the SCP0MD0 and
SCP0MD1 bits. When the TxD pin is set to output mode, the value of the SCP0DT bit is output to
the TxD pin. The RxD pin value is read from the SCP0DT bit regardless of the values of the
SCP0MD0 and SCP0MD1 bits, if RE in SCSCR is set to 1. The initial value of this bit after a
power-on reset is undefined.
Block diagrams of the SCI I/O port pins are shown in figures 15.2, 15.3, and 15.4.
15.2.9
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset, and in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
The SCBRR setting is calculated as follows:
Bit 0:
SCP0DT
0
1
Initial value:
B:
N:
P : Operating frequency for peripheral modules (MHz)
n:
Asynchronous mode: N
Synchronous mode: N
Bit Rate Register (SCBRR)
R/W:
Bit rate (bits/s)
SCBRR setting for baud rate generator (0
Baud rate generator clock source (n
n, see table 15.3.)
Bit:
Description
I/O data is low
I/O data is high
R/W
7
1
R/W
6
1
64
8
2
2
2n – 1
R/W
P
P
2n – 1
5
1
B
B
0, 1, 2, 3) (for the clock sources and values of
R/W
4
1
10
10
N
6
6
– 1
– 1
255)
R/W
3
1
Rev. 5.0, 09/03, page 489 of 806
R/W
2
1
R/W
1
1
(Initial value)
R/W
0
1
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