D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 18

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section
21.3 Bus Master
Interface
Figure 21.2 A/D Data
Register Access
Operation (Reading
H'AA40)
24.1 Absolute
Maximum Ratings
Table 24.1 Absolute
Maximum Ratings
24.2 DC
Characteristics
Table 24.2 DC
Characteristics
Rev. 5.0, 09/03, page xvi of xlvi
Page
665
701
703,
705
Description
Figure amended
Upper byte read
Lower byte read
Caution amended
2.Until voltage is applied to all power supplies, a low level is input
at the RESETP pin, and CKIO has operated for a maximum of 4
clock cycles, internal circuits remain unsettled, and so pin states
are also undefined. The system design must ensure that these
undefined states do not cause erroneous system operation.
Note that the RESETP pin cannot receive a low level signal while
a low level signal is being input to the CA pin.
Test conditions for in sleep mode amended
Item
In sleep
mode *
Note * added
*
data H'AA
data H'40
receives
receives
If the IRL and IRLS interrupts are used, the minimum is 1.9 V.
CPU
CPU
1
Symbol Min
Icc
—
interface
interface
Bus
Bus
Typ Max Unit
15
ADDRn H
ADDRn H
30
[H'AA]
[H'AA]
Module internal data bus
Module internal data bus
ADDRn L
ADDRn L
Test Conditions
*
Vcc = 1.9 V
VccQ = 3.3 V
B = 33 MHz
TEMP
TEMP
[H'40]
[H'40]
[H'40]
[H'40]
1
: No external bus
cycles
except refresh
cycles
n = A to D
n = A to D