D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 37

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 11.16 Basic Timing for Synchronous DRAM Single Read............................................ 328
Figure 11.17 Basic Timing for Synchronous DRAM Burst Write ............................................ 330
Figure 11.18 Basic Timing for Synchronous DRAM Single Write........................................... 332
Figure 11.19 Burst Read Timing (No Precharge) ...................................................................... 335
Figure 11.20 Burst Read Timing (Same Row Address) ............................................................ 336
Figure 11.21 Burst Read Timing (Different Row Addresses) ................................................... 337
Figure 11.22 Burst Write Timing (No Precharge) ..................................................................... 338
Figure 11.23 Burst Write Timing (Same Row Address) ........................................................... 339
Figure 11.24 Burst Write Timing (Different Row Addresses) .................................................. 340
Figure 11.25 Auto-Refresh Operation ....................................................................................... 341
Figure 11.26 Synchronous DRAM Auto-Refresh Timing......................................................... 342
Figure 11.27 Synchronous DRAM Self-Refresh Timing .......................................................... 344
Figure 11.28 Synchronous DRAM Mode Write Timing ........................................................... 346
Figure 11.29 Burst ROM Wait Access Timing ......................................................................... 348
Figure 11.30 Burst ROM Basic Access Timing ........................................................................ 349
Figure 11.31 Example of PCMCIA Interface ............................................................................ 351
Figure 11.32 Basic Timing for PCMCIA Memory Card Interface ............................................ 353
Figure 11.33 Wait Timing for PCMCIA Memory Card Interface ............................................. 354
Figure 11.34 Basic Timing for PCMCIA Memory Card Interface Burst Access ...................... 355
Figure 11.35 Wait Timing for PCMCIA Memory Card Interface Burst Access ....................... 356
Figure 11.36 PCMCIA Space Allocation .................................................................................. 357
Figure 11.37 Basic Timing for PCMCIA I/O Card Interface .................................................... 359
Figure 11.38 Wait Timing for PCMCIA I/O Card Interface ..................................................... 360
Figure 11.39 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ............................ 361
Figure 11.40 Waits between Access Cycles .............................................................................. 363
Figure 11.41 Pull-Up Timing for Pins A25 to A0 ..................................................................... 364
Figure 11.42 Pull-Up Timing for Pins D31 to D0 (Read Cycle) ............................................... 365
Figure 11.43 Pull-Up Timing for Pins D31 to D0 (Write Cycle) .............................................. 365
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Figure 12.5
Figure 12.6
Figure 12.7
Figure 12.8
Figure 12.9
Block Diagram of DMAC .................................................................................... 371
DMAC Transfer Flowchart .................................................................................. 388
Round-Robin Mode.............................................................................................. 392
Changes in Channel Priority in Round-Robin Mode............................................ 393
Operation of Direct Address Mode in Dual Address Mode ................................. 395
Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode
(Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory). 396
Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode
(16-byte Transfer, Transfer Source: Ordinary Memory,
Transfer Destination: Ordinary Memory)............................................................. 397
Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode
(16-byte Transfer, Transfer Source: Synchronous DRAM,
Transfer Destination: Ordinary Memory)............................................................. 397
Indirect Address Operation in Dual Address Mode (When External Memory
Space has a 16-Bit Width).................................................................................... 399
Rev. 5.0, 09/03, page xxxv of xlvi