D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 617
![IC SUPER H MPU ROMLESS 208QFP](/photos/12/31/123145/d6417729rhf200bv_sml.jpg)
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Bit 3—Framing Error (FER): Indicates a framing error in the data read from the receive FIFO
data register (SCFRDR).
Bit 2—Parity Error (PER): Indicates a parity error in the data read from the receive FIFO data
register (SCFRDR).
Bit 1—Receive FIFO Data Full (RDF): Indicates that receive data has been transferred to the
receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become equal or
greater than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO
control register (SCFCR).
Note: * Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be read
Bit 3: FER
0
1
Bit 2: PER
0
1
Bit 1: RDF
0
1
when RDF is 1 is the specified receive trigger number. If an attempt is made to read after
all the data in SCFRDR has been read, the data is undefined. The quantity of receive data
in SCFRDR is indicated by the lower 8 bits of SCFTDR.
Description
No receive framing error occurred in the data read from SCFRDR (Initial value)
FER is cleared to 0 when the chip undergoes a power-on reset or enters standby
mode, or when no framing error is present in the data read from SCFRDR
A receive framing error occurred in the data read from SCFRDR
FER is set to 1 when a framing error is present in the data read from SCFRDR
Description
No receive parity error occurred in the data read from SCFRDR
PER is cleared to 0 when the chip undergoes a power-on reset or enters standby
mode, or when no parity error is present in the data read from SCFRDR
A receive framing error occurred in the data read from SCFRDR
PER is set to 1 when a parity error is present in the data read from SCFRDR
Description
The quantity of transmit data written to SCFRDR is less than the specified
receive trigger number
When, after a power-on reset or in the standby mode, the quantity of receive
data in SCFRDR is less than the specified receive trigger value and 1 is read
from RDF, which is then cleared to 0
The quantity of receive data in SCFRDR is equal or greater than the specified
receive trigger number
RDF is set to 1 when a quantity of receive data equal or greater than the
specified receive trigger number is stored in SCFRDR *
Rev. 5.0, 09/03, page 569 of 806
(Initial value)
(Initial value)
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