D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 612

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): Select the internal clock source of the on-
chip baud rate generator. Four clock sources are available. P , P /4, P /16 and P /64. For further
information on the clock source, bit rate register settings, and baud rate, see section 17.2.8, Bit
Rate Register (SCBRR).
Bit 1: CKS1
0
1
Note: P : Peripheral clock
17.2.6
The serial control register (SCSCR) operates the SCIF transmitter/receiver, selects the serial clock
output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive
clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'00 by a
reset and in standby or module standby mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-FIFO-data-empty
interrupt (TXI) requested when the serial transmit data is transferred from the transmit FIFO data
register (SCFTDR) to the transmit shift register (SCTSR), when the quantity of data in the
transmit FIFO register becomes less than the specified number of transmission triggers, and when
the TDFE flag in the serial FIFO status register (SCFSR) is set to1.
Bit 7: TIE
0
1
Rev. 5.0, 09/03, page 564 of 806
Initial value:
Serial Control Register (SCSCR)
R/W:
Bit:
Bit 0: CKS0
0
1
0
1
Description
Transmit-FIFO-data-empty interrupt request (TXI) is disabled
The TXI interrupt request can be cleared by writing a greater quantity of transmit
data than the specified transmission trigger number to SCFTDR and by clearing
TDFE to 0 after reading 1 from TDFE, or can be cleared by clearing TIE to 0.
Transmit-FIFO-data-empty interrupt request (TXI) is enabled
R/W
TIE
7
0
R/W
RIE
6
0
Description
P
P /4
P /16
P /64
R/W
TE
5
0
R/W
RE
4
0
—
R
3
0
—
R
2
0
CKE1
R/W
1
0
(Initial value)
(Initial value)
CKE0
R/W
0
0