D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 642

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

17.4
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),
receive-data-full (RXI), and break (BRI).
Table 17.10 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE and RIE bits in SCSCR. A separate interrupt request is
sent to the interrupt controller for each of these interrupt sources.
When the TDFE flag in the serial status register (SCSSR) is set to 1, a TXI interrupt request is
generated. The DMAC can be activated and data transfer performed when this interrupt is
generated. When data exceeding the transmit trigger number is written to the transmit data
register (SCFTDR) by the DMAC, 1 is read from the TDFE flag, after which 0 is written to it to
clear it.
When the RDF flag in SCSSR is set to 1, an RXI interrupt request is generated. The DMAC can
be activated and data transfer performed when the RDF flag in SCSSR is set to 1. When receive
data less than the receive trigger number is read from the receive data register (SCFRDR) by the
DMAC, 1 is read from the RDF flag, after which 0 is written to it to clear it.
When the ER flag in SCSSR is set to 1, an ERI interrupt request is generated.
When the BRK flag in SCSSR is set to 1, a BRI interrupt request is generated.
The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that
there is receive data in SCFRDR.
Table 17.10 SCIF Interrupt Sources
Interrupt
Source
ERI
RXI
BRI
TXI
See section 4, Exception Handling, for priorities and the relationship to non-SCIF interrupts.
Rev. 5.0, 09/03, page 594 of 806
SCIF Interrupts
Description
Interrupt initiated by receive error flag (ER)
Interrupt initiated by receive data FIFO full flag
(RDF) or data ready flag (DR)
Interrupt initiated by break flag (BRK)
Interrupt initiated by transmit FIFO data empty flag
(TDFE)
DMAC
Activation
Possible
(RDF only)
Possible
Not possible
Not possible
Priority
High
Low