D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 22

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3.4
3.5
3.6
3.7
Section 4 Exception Handling
4.1
4.2
4.3
4.4
4.5
Rev. 5.0, 09/03, page xx of xlvi
3.3.1
3.3.2
3.3.3
3.3.4
MMU Functions ................................................................................................................ 105
3.4.1
3.4.2
3.4.3
3.4.4
MMU Exceptions .............................................................................................................. 110
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
Memory-Mapped TLB ...................................................................................................... 118
3.6.1
3.6.2
3.6.3
Usage Note ........................................................................................................................ 121
Overview ........................................................................................................................... 123
4.1.1
4.1.2
Exception Handling Function............................................................................................ 123
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
Register Descriptions......................................................................................................... 130
Exception Handling Operation .......................................................................................... 131
4.4.1
4.4.2
4.4.3
Individual Exception Operations ....................................................................................... 132
4.5.1
4.5.2
4.5.3
Configuration of the TLB ..................................................................................... 99
TLB Indexing ....................................................................................................... 101
TLB Address Comparison.................................................................................... 102
Page Management Information ............................................................................ 104
MMU Hardware Management ............................................................................. 105
MMU Software Management............................................................................... 105
MMU Instruction (LDTLB) ................................................................................. 106
Avoiding Synonym Problems............................................................................... 107
TLB Miss Exception ............................................................................................ 110
TLB Protection Violation Exception.................................................................... 111
TLB Invalid Exception......................................................................................... 112
Initial Page Write Exception ................................................................................ 113
Processing Flow in Event of MMU Exception
(Same Processing Flow for Address Error) .......................................................... 115
MMU Exception in Repeat Loop ......................................................................... 117
Address Array ...................................................................................................... 118
Data Array ............................................................................................................ 119
Usage Examples ................................................................................................... 121
Features ................................................................................................................ 123
Register Configuration ......................................................................................... 123
Exception Handling Flow..................................................................................... 123
Exception Vector Addresses................................................................................. 124
Acceptance of Exceptions .................................................................................... 126
Exception Codes................................................................................................... 128
Exception Request Masks .................................................................................... 129
Returning from Exception Handling .................................................................... 129
Reset..................................................................................................................... 131
Interrupts .............................................................................................................. 131
General Exceptions............................................................................................... 132
Resets ................................................................................................................... 132
General Exceptions............................................................................................... 133
Interrupts .............................................................................................................. 138
.......................................................................................... 123