D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 692

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

20.8.2
Note: * Undefined
The port G data register (PGDR) is an 8-bit read-only register that stores data for pins PTG7 to
PTG0. Bits PG7DT to PG0DT correspond to pins PTG7 to PTG0. When the function is general
input port, if the port is read the corresponding pin level is read. Table 20.14 shows the function of
PGDR.
PGDR is initialized by a power-on reset, after which the general input port function (pull-up MOS
on) is set as the initial pin function, and the corresponding pin levels are read.
Table 20.14 Port G Data Register (PGDR) Read/Write Operations
PGnMD1
0
1
Rev. 5.0, 09/03, page 644 of 806
Initial value:
Port G Data Register (PGDR)
PGnMD0 Pin State
0
1
0
1
R/W:
Bit:
PG7DT
Other function
(See table 19.1)
Reserved
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
R
7
*
PG6DT
R
6
*
PG5DT
H'00
Read
H'00
Pin state
Pin state
R
5
*
PG4DT
R
4
*
Write
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
PG3DT
R
3
*
PG2DT
R
2
*
PG1DT
R
1
*
(n = 0 to 7)
PG0DT
R
0
*