D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 710

• Manufacturer Part Number: D6417729RHF200BV
• Description: IC SUPER H MPU ROMLESS 208QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417729RHF200BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

21.2.2
Note: * Write 0 to clear the flag.
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7: ADF
0
1
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion.
Bit 6: ADIE
0
1
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.
Bit 5: ADST
0
1
Rev. 5.0, 09/03, page 662 of 806
Initial value:
A/D Control/Status Register (ADCSR)
R/W:
Bit:
Description
[Clearing conditions]
(1) Cleared by reading ADF while ADF = 1, then writing 0 to ADF
(2) Cleared when DMAC is activated by ADI interrupt and ADDR is read
[Setting conditions]
Single mode: A/D conversion ends
Multi mode: A/D conversion ends on all selected channels
Description
A/D end interrupt request (ADI) is disabled
A/D end interrupt request (ADI) is enabled
Description
A/D conversion is stopped
Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends
Scan mode: A/D conversion starts and continues, cycling through the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a transition to
standby mode
R/(W) *
ADF
7
0
ADIE
R/W
6
0
ADST
R/W
5
0
MULTI
R/W
4
0
CKS
R/W
3
0
CH2
R/W
2
0
CH1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
CH0
R/W
0
0