AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 259
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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20. Synchronous Serial Controller (SSC)
20.1
20.2
32059K–03/2011
Features
Overview
Rev: 3.1.0.2
•
•
•
•
•
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The Synchronous Serial Controller (SSC) provides a synchronous communication link with
external devices. It supports many serial synchronous communication protocols generally used
in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.
The SSC consists of a receiver, a transmitter, and a common clock divider. Both the receiver
and the transmitter interface with three signals:
The transfers can be programmed to start automatically or on different events detected on the
Frame Sync signal.
The SSC’s high-level of programmability and its two dedicated Peripheral DMA Controller chan-
nels of up to 32 bits permit a continuous high bit rate data transfer without processor
intervention.
Featuring connection to two Peripheral DMA Controller channels, the SSC permits interfacing
with low processor overhead to the following:
• the TX_DATA/RX_DATA signal for data
• the TX_CLOCK/RX_CLOCK signal for the clock
• the TX_FRAME_SYNC/RX_FRAME_SYNC signal for the frame synchronization
• CODEC’s in master or slave mode
• DAC through dedicated serial interface, particularly I2S
• Magnetic card reader
Provides serial synchronous communication links used in audio and telecom applications
Independent receiver and transmitter, common clock divider
Interfaced with two Peripheral DMA Controller channels to reduce processor overhead
Configurable frame sync and data length
Receiver and transmitter can be configured to start automatically or on detection of different
events on the frame sync signal
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
AT32UC3B
259
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