AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 280
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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20.9.4
Name:
Access Type:
Offset:
Reset value:
• FSLENHI: Receive Frame Sync Length High Part
• FSEDGE: Receive Frame Sync Edge Detection
• FSOS: Receive Frame Sync Output Selection
• FSLEN: Receive Frame Sync Length
32059K–03/2011
MSBF
FSEDGE
31
23
15
Others
FSOS
7
-
-
The four MSB of the FSLEN field.
Determines which edge on Frame Sync will generate the SR.RXSYN interrupt.
This field defines the length of the Receive Frame Sync signal and the number of bits sampled and stored in the RSHR register.
When this mode is selected by the RCMR.START field, it also determines the length of the sampled data to be compared to the
Compare 0 or Compare 1 register.
Note: The four most significant bits for this field are located in the FSLENHI field.
The pulse length is equal to ({FSLENHI,FSLEN} + 1) receive clock periods. Thus, if {FSLENHI,FSLEN} is zero, the Receive
Frame Sync signal is generated during one receive clock period.
0
1
2
3
4
5
0
1
Receive Frame Mode Register
Selected Receive Frame Sync Signal
Frame Sync Edge Detection
Positive edge detection
Negative edge detection
None
Negative Pulse
Positive Pulse
Driven Low during data transfer
Driven High during data transfer
Toggling at each start of data transfer
Reserved
30
22
14
6
-
-
RFMR
Read/Write
0x14
0x00000000
FSLENHI
FSOS
LOOP
29
21
13
5
-
28
20
12
4
-
27
19
11
3
-
RX_FRAME_SYNC Pin
Undefined
Input-only
DATLEN
Output
Output
Output
Output
Output
26
18
10
2
-
FSLEN
DATNB
25
17
9
1
-
AT32UC3B
FSEDGE
24
16
8
0
280
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