AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 396

• Manufacturer Part Number: AT32UC3B0512-A2UT
• Description: IC MCU AVR32 512K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-A2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Controller Family/series: AT32UC3B
• No. Of I/o's: 44
• Ram Memory Size: 96KB
• Cpu Speed: 60MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.7.3.12
22.7.3.13
32059K–03/2011
TXOUTI
FIFOCON
CRC error
Interrupts
•Global interrupts
•Pipe interrupts
SW
Figure 22-29. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay
This error exists only for isochronous IN pipes. It set the CRC Error Interrupt (CRCERRI) bit,
what triggers a PnINT interrupt if then the CRC Error Interrupt Enable (CRCERRE) bit in
UPCONn is one.
A CRC error can occur during IN stage if the USBB detects a corrupted received packet. The IN
packet is stored in the bank as if no CRC error had occurred (RXINI is set).
See the structure of the USB host interrupt system on
There are two kinds of host interrupts: processing, i.e. their generation is part of the normal pro-
cessing, and exception, i.e. errors (not related to CPU exceptions).
The processing host global interrupts are:
There is no exception host global interrupt.
The processing host pipe interrupts are:
write data to CPU
• The Device Connection Interrupt (DCONNI)
• The Device Disconnection Interrupt (DDISCI)
• The USB Reset Sent Interrupt (RSTI)
• The Downstream Resume Sent Interrupt (RSMEDI)
• The Upstream Resume Received Interrupt (RXRSMI)
• The Host Start of Frame Interrupt (HSOFI)
• The Host Wake-Up Interrupt (HWUPI)
• The Pipe n Interrupt (PnINT)
• The DMA Channel n Interrupt (DMAnINT)
• The Received IN Data Interrupt (RXINI)
BANK 0
SW
OUT
SW
write data to CPU
BANK 1
(bank 0)
DATA
SW
ACK
HW
Figure 22-6 on page
SW
OUT
write data to CPU
BANK0
(bank 1)
DATA
AT32UC3B
371.
ACK
396