AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 450

• Manufacturer Part Number: AT32UC3B0512-A2UT
• Description: IC MCU AVR32 512K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-A2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Controller Family/series: AT32UC3B
• No. Of I/o's: 44
• Ram Memory Size: 96KB
• Cpu Speed: 60MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.8.2.20
Register Name:
Access Type:
Offset:
Reset Value:
• CHBYTECNT: Channel Byte Count
• DESCLDSTA: Descriptor Loaded Status
• EOCHBUFFSTA: End of Channel Buffer Status
• EOTSTA: End of USB Transfer Status
• CHACTIVE: Channel Active
• CHEN: Channel Enabled
32059K–03/2011
31
23
15
7
-
-
This field contains the current number of bytes still to be transferred for this buffer.
This field is decremented at each dma access.
This field is reliable (stable) only if the CHEN bit is zero.
This bit is set when a Descriptor has been loaded from the HSB bus.
This bit is cleared when read by the user.
This bit is set when the Channel Byte Count counts down to zero.
This bit is automatically cleared when read by software.
This bit is set when the completion of the usb data transfer has closed the dma transfer. It is valid only if
UDDMAnCONTROL.BUFFCLOSEINEN is one.
This bit is automatically cleared when read by software.
0: the DMA channel is no longer trying to source the packet data.
1: the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. When a
packet transfer cannot be completed due to an EOCHBUFFSTA, this bit stays set during the next channel descriptor load (if any)
and potentially until USB packet transfer completion, if allowed by the new descriptor.
When programming a DMA by descriptor (Load next descriptor now), the CHACTIVE bit is set only once the DMA is running
(the endpoint is free for IN transaction, the endpoint is full for OUT transaction).
This bit is set (after one cycle latency) when the L.CHEN is written to one or when the descriptor is loaded.
This bit is cleared when any transfer is ended either due to an elapsed byte count or a USB device initiated transfer end.
0: the DMA channel no longer transfers data, and may load the next descriptor if the UDDMAnCONTROL.LDNXTCHDESCEN
bit is zero.
Device DMA Channel n Status Register
DESCLD
STA
30
22
14
6
-
UDDMAnSTATUS, n in [1..6]
Read/Write
0x031C + (n - 1) * 0x10
0x00000000
EOCHBUFF
STA
29
21
13
5
-
EOTSTA
CHBYTECNT[15:8]
28
20
12
CHBYTECNT[7:0]
4
-
27
19
11
3
-
-
26
18
10
2
-
-
CHACTIVE
25
17
9
1
-
AT32UC3B
CHEN
24
16
8
0
-
450