AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 437

• Manufacturer Part Number: AT32UC3B0512-A2UT
• Description: IC MCU AVR32 512K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-A2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Controller Family/series: AT32UC3B
• No. Of I/o's: 44
• Ram Memory Size: 96KB
• Cpu Speed: 60MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• CURRBK: Current Bank
• NBUSYBK: Number of Busy Banks
• DTSEQ: Data Toggle Sequence
• SHORTPACKET: Short Packet Interrupt
32059K–03/2011
This bit is set for non-control endpoints, to indicate the current bank:
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
This field is set to indicate the number of busy banks:
For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this
triggers an EPnINT interrupt if NBUSYBKE is one.
For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this
triggers an EPnINT interrupt if NBUSYBKE is one.
When the FIFOCON bit is cleared (by writing a one to the FIFOCONC bit) to validate a new bank, this field is updated two or
three clock cycles later to calculate the address of the next bank.
An EPnINT interrupt is triggered if:
- for IN endpoint, NBUSYBKE is one and all the banks are free.
- for OUT endpoint, NBUSYBKE is one and all the banks are busy.
This field is set to indicate the PID of the current bank:
For IN transfers, it indicates the data toggle sequence that will be used for the next packet to be sent. This is not relative to the
current bank.
For OUT transfers, this value indicates the last data toggle sequence received on the current bank.
By default DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence
should be Data0.
This bit is set for non-control OUT endpoints, when a short packet has been received.
0
0
1
1
0
0
1
1
0
0
1
NBUSYBK
CURRBK
DTSEQ
X
0
1
0
1
0
1
0
1
0
1
Current Bank
Bank0
Bank1
Bank2 if supported
Reserved
Number of Busy Banks
0 (all banks free)
1
2
3 if supported
Data Toggle Sequence
Data0
Data1
Reserved
(see
(see
Table 22-1 on page
Table 22-1 on page
362).
362).
AT32UC3B
437