AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 388
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
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Part Number:
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Manufacturer:
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22.7.2.14
22.7.2.15
22.7.2.16
22.7.2.17
32059K–03/2011
Underflow
Overflow
CRC error
Interrupts
•Global interrupts
This error exists only for isochronous IN/OUT endpoints. It set the Underflow Interrupt
(UNDERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Underflow Interrupt Enable
(UNDERFE) bit is one.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-
length packet is then automatically sent by the USBB.
An underflow can not occur during OUT stage on a CPU action, since the user may read only if
the bank is not empty (RXOUTI is one or RWALL is one).
An underflow can also occur during OUT stage if the host sends a packet while the bank is
already full. Typically, the CPU is not fast enough. The packet is lost.
An underflow can not occur during IN stage on a CPU action, since the user may write only if the
bank is not full (TXINI is one or RWALL is one).
This error exists for all endpoint types. It set the Overflow interrupt (OVERFI) bit in UESTAn,
what triggers an EPnINT interrupt if the Overflow Interrupt Enable (OVERFE) bit is one.
An overflow can occur during OUT stage if the host attempts to write into a bank that is too small
for the packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had
occurred. The bank is filled with all the first bytes of the packet that fit in.
An overflow can not occur during IN stage on a CPU action, since the user may write only if the
bank is not full (TXINI is one or RWALL is one).
This error exists only for isochronous OUT endpoints. It set the CRC Error Interrupt (CRCERRI)
bit in UESTAn, what triggers an EPnINT interrupt if the CRC Error Interrupt Enable (CRCERRE)
bit is one.
A CRC error can occur during OUT stage if the USBB detects a corrupted received packet. The
OUT packet is stored in the bank as if no CRC error had occurred (RXOUTI is set).
See the structure of the USB device interrupt system on
There are two kinds of device interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors (not related to CPU exceptions).
The processing device global interrupts are:
• The Suspend (SUSP) interrupt
• The Start of Frame (SOF) interrupt with no frame number CRC error (the Frame Number
• The End of Reset (EORST) interrupt
• The Wake-Up (WAKEUP) interrupt
• The End of Resume (EORSM) interrupt
CRC Error (FNCERR) bit in the Device Frame Number (UDFNUM) register is zero)
Figure 22-6 on page
AT32UC3B
371.
388
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