AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 383
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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•Control read
USB Bus
RXSTPI
RXOUTI
TXINI
Wr Enable
HOST
Wr Enable
CPU
Figure 22-15. Control Write
Figure 22-16 on page 383
simultaneous write requests from the CPU and the USB host.
Figure 22-16. Control Read
A NAK handshake is always generated on the first status stage command.
When the controller detects the status stage, all the data written by the CPU are lost and clear-
ing TXINI has no effect.
The user checks if the transmission or the reception is complete.
The OUT retry is always ACKed. This reception sets RXOUTI and TXINI. Handle this with the
following software algorithm:
Once the OUT status stage has been received, the USBB waits for a SETUP request. The
SETUP request has priority over any other request and has to be ACKed. This means that any
other bit should be cleared and the FIFO reset when a SETUP is received.
The user has to take care of the fact that the byte counter is reset when a zero-length OUT
packet is received.
USB Bus
RXSTPI
RXOUTI
TXINI
set TXINI
wait for RXOUTI OR TXINI
if RXOUTI, then clear bit and return
if TXINI, then continue
SETUP
SETUP
HW
SETUP
SETUP
HW
SW
SW
SW
IN
shows a control read transaction. The USBB has to manage the
HW
OUT
HW
DATA
SW
IN
SW
DATA
OUT
HW
OUT
NAK
SW
STATUS
NAK
IN
AT32UC3B
STATUS
OUT
SW
HW
IN
SW
383
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