AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 331
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
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Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
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Quantity:
20 000
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21.6.8.2
32059K–03/2011
Baud Rate
In SPI Mode, the baudrate generator operates in the same way as in USART synchronous
mode:
In SPI Master Mode:
In SPI Slave Mode:
• the external clock CLK must not be selected (USCLKS … 0x3), and the bit CLKO must be set
• to obtain correct behavior of the receiver and the transmitter, the value programmed in CD of
• if the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must
• the external clock (CLK) selection is forced regardless of the value of the USCLKS field in the
• to obtain correct behavior of the receiver and the transmitter, the external clock (CLK)
to “1” in the Mode Register (MR), in order to generate correctly the serial clock on the CLK
pin.
must be superior or equal to 4.
be even to ensure a 50:50 mark/space ratio on the CLK pin, this value can be odd if the
internal clock is selected (CLK_USART).
Mode Register (MR). Likewise, the value written in BRGR has no effect, because the clock is
provided directly by the signal on the USART CLK pin.
frequency must be at least 4 times lower than the system clock.
See Section “21.6.1.4” on page 304.
However, there are some restrictions:
AT32UC3B
331
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