AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 311

• Manufacturer Part Number: AT32UC3B0512-A2UT
• Description: IC MCU AVR32 512K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-A2UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Controller Family/series: AT32UC3B
• No. Of I/o's: 44
• Ram Memory Size: 96KB
• Cpu Speed: 60MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.6.3.4
32059K–03/2011
Manchester Decoder
Figure 21-11. Asynchronous Start Detection
Figure 21-12. Asynchronous Character Reception
When the MAN field in MR register is set to 1, the Manchester decoder is enabled. The decoder
performs both preamble and start frame delimiter detection. One input line is dedicated to Man-
chester encoded input data.
An optional preamble sequence can be defined, its length is user-defined and totally indepen-
dent of the emitter side. Use RX_PL in MAN register to configure the length of the preamble
sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addi-
tion, the polarity of the input stream is programmable with RX_MPOL field in MAN register.
Depending on the desired application the preamble pattern matching is to be defined via the
RX_PP field in MAN. See
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder.
So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start
frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame
delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled dur-
ing one quarter of a bit time at zero, a start bit is detected. See
rejection mechanism applies.
Clock (x16)
Baud Rate
Sampling
Sampling
Sampling
Baud Rate
Example: 8-bit, Parity Enabled
Detection
Clock
RXD
RXD
Start
Clock
RXD
1
1
2
2
samples
3
3
16
4
4
Figure 21-8
D0
5
5
samples
16
6
6
D1
7
Detection
7
Rejection
samples
Start
Start
16
8
0
for available preamble patterns.
D2
1
1
samples
16
2
2
3
3
D3
samples
4
4
16
5
D4
samples
6
16
7
D5
samples
8
16
Figure
9 10 11 12 13 14 15 16
D6
samples
16
21-13. The sample pulse
D7
samples
AT32UC3B
16
Parity
Bit
samples
16
Stop
Bit
Sampling
D0
311