AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 400
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 400 of 692
- Download datasheet (11Mb)
32059K–03/2011
•Single-block transfer programming example for OUT transfer :
•Programming example for single-block dma transfer with automatic closure for OUT transfer :
The following sequence may be used:
The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable.
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
nation address until the endpoint is empty or the channel byte length is reached. Once the
endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared.
Once the DMA channel is completed (i.e : the channel byte length is reached), after one or mul-
tiple processed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence,
the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTATUS.EOCHBUFFSTA bit
is set indicating a end of dma channel. If the UDDMAnCONTROL.DMAENDEN bit was set, the
last endpoint bank will be properly released even if there are some residual datas inside, i.e:
OUT packet truncation at the end of DMA buffer when the dma channel byte lenght is not an
integral multiple of the endpoint size.
The idea is to automatically close the DMA transfer at the end of the OUT transaction (received
short packet). The following sequence may be used:
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
n a t i o n a d d r e s s u n t i l t h e e n d p o i n t i s e m p t y . O n c e t h e e n d p o i n t i s e m p t y , t h e
UDDMAnSTATUS.CHACTIVE bit is cleared.
After one or multiple processed OUT packet, the DMA channel is completed after sourcing a
short packet. Then, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, after a few
cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTA-
TUS.EOTSTA bit is set indicating that the DMA was closed by a end of USB transaction.
• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching
• Write the starting destination address in the UDDMAnADDR register.
• There is no need to program the UDDMAnNEXTDESC register.
• Program the channel byte length in the UDDMAnCONTROL register.
• Program the UDDMAnCONTROL according to Row 2 as shown in
• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching
• Write the starting destination address in the UDDMAnADDR register.
• There is no need to program the UDDMAnNEXTDESC register.
• Program the channel byte length in the UDDMAnCONTROL register.
• Set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register.
• Program the UDDMAnCONTROL according to Row 2 as shown in
for this endpoint in the UECFGn register to handle multiple OUT packet.
to set up a single block transfer.
for this endpoint in the UECFGn register to handle multiple OUT packet.
to set up a single block transfer.
Figure 22-6 on page 449
Figure 22-6 on page 449
AT32UC3B
400
Related parts for AT32UC3B0512-A2UT
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
DEV KIT FOR AVR/AVR32
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Monolithic Integrated Feature Phone Circuit
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Multistandard Video-IF and Quasi Parallel Sound Processing
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
High-performance EE PLD
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
8-bit Flash Microcontroller
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
2-Wire Serial EEPROM
Manufacturer:
ATMEL Corporation
Datasheet: