AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 677
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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- Download datasheet (11Mb)
32059K–03/2011
- Power Manager
- SSC
3. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first
4. SPI CSNAAT bit 2 in register CSR0...CSR3 is not available
5. SPI disable does not work in SLAVE mode
1. PLL Lock control does not work
2. Wrong reset causes when BOD is activated
3. System Timer mask (Bit 16) of the PM CPUMASK register is not available
1. SSC does not trigger RF when data is low
transfer
In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or
during the first transfer.
Fix/Workaround
1. Set slave mode, set required CPOL/CPHA.
2. Enable SPI.
3. Set the polarity CPOL of the line in the opposite value of the required one.
4. Set the polarity CPOL to the required one.
5. Read the RXHOLDING register.
Transfers can now befin and RXREADY will now behave as expected.
SPI CSNAAT bit 2 in register CSR0...CSR3 is not available.
Fix/Workaround
Do not use this bit.
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a Software Reset.
PLL lock Control does not work.
Fix/Workaround
In PLL Control register, the bit 7 should be set in order to prevent unexpected behaviour.
Setting the BOD enable fuse will cause the Reset Cause Register to list BOD reset as the
reset source even though the part was reset by another source.
Fix/Workaround
Do not set the BOD enable fuse, but activate the BOD as soon as your program starts.
System Timer mask (Bit 16) of the PM CPUMASK register is not available.
Fix/Workaround
Do not use this bit.
The SSC cannot transmit or receive data when CKS = CKDIV and CKO = none, in TCMR or
RCMR respectively.
Fix/Workaround
Set CKO to a value that is not "none" and bypass the output of the TK/RK pin with the GPIO.
AT32UC3B
677
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