ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 126

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.16.1
10.16.1.1
10.16.1.2
10.16.1.3
10.16.1.4
10.16.1.5
126
BFC
BFI
SAM3S Preliminary
BFC and BFI
Syntax
Operation
Restrictions
Condition flags
Examples
R4, #8, #12
R9, R2, #8, #12
Bit Field Clear and Bit Field Insert.
where:
cond
Rd
Rn
lsb
width
BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb.
Other bits in Rd are unchanged.
BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at
the low bit position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged.
Do not use SP and do not use PC.
These instructions do not affect the flags.
BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width
; Clear bit 8 to bit 19 (12 bits) of R4 to 0
; Replace bit 8 to bit 19 (12 bits) of R9 with
; bit 0 to bit 11 from R2
is an optional condition code, see
is the destination register.
is the source register.
is the position of the least significant bit of the bitfield.
lsb must be in the range 0 to 31.
is the width of the bitfield and must be in the range 1 to 32− lsb.
“Conditional execution” on page
6500C–ATARM–8-Feb-11
84.