ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 48

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.4.3.8
• ICI
Interruptible-continuable instruction bits, see
• IT
Indicates the execution state bits of the
• T
Always set to 1.
10.4.3.9
10.4.3.10
10.4.3.11
48
SAM3S Preliminary
Execution Program Status Register
Interruptible-continuable instructions
If-Then block
Exception mask registers
The EPSR contains the Thumb state bit, and the execution state bits for either the:
See the register summary in
ments are:
Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are ignored. Fault handlers can examine EPSR value in the stacked PSR to indicate the opera-
tion that is at fault. See
When an interrupt occurs during the execution of an LDM or STM instruction, the processor:
After servicing the interrupt, the processor:
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruc-
tion in the block is conditional. The conditions for the instructions are either all the same, or
some can be the inverse of others. See
The exception mask registers disable the handling of exceptions by the processor. Disable
exceptions where they might impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruc-
tion to change the value of PRIMASK or FAULTMASK. See
144, and
• If-Then (IT) instruction
• Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store
• stops the load multiple or store multiple instruction operation temporarily
• stores the next register operand in the multiple operation to EPSR bits[15:12].
• returns to the register pointed to by bits[15:12]
• resumes execution of the multiple load or store instruction.
multiple instruction.
“CPS” on page 139
IT
instruction, see
“Interruptible-continuable instructions” on page
“Exception entry and return” on page 68
for more information.
Table 10-2 on page 44
“IT” on page
“IT” on page 133
133.
for the EPSR attributes. The bit assign-
for more information.
“MRS” on page
48.
143,
6500C–ATARM–8-Feb-11
“MSR” on page