ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 996

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

39.7.3
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• USCHx: User Sequence Number x
The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this
field. The allowed range is 0 up to 3. So it is only possible to use the sequencer from CH0 to
This register activates only if ADC_MR(USEQ) field is set to ‘1’.
Any USCHx field is taken into account only if ADC_CHSR(CHx) register field reads logical ‘1’ else any value written in
USCHx does not add the corresponding channel in the conversion sequence.
When configuring consecutive fields with the same value, the associated channel is sampled as many time as the number
of consecutive values, this part of the conversion sequence being triggered by a unique event.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion
sequence. This can be done consecutively, or not, according to user needs.
996
996
31
23
15
–
–
–
7
–
SAM3S Preliminary
SAM3S Preliminary
ADC Channel Sequence 1 Register
30
22
14
ADC_SEQR1
0x40038008
Read-write
6
USCH8
USCH6
USCH4
USCH2
29
21
13
5
28
20
12
4
“ADC Write Protect Mode Register” on page
27
19
11
–
–
–
3
–
26
18
10
2
CH3.
USCH7
USCH5
USCH3
USCH1
25
17
9
1
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
1013.
24
16
8
0